1. Field of the Invention
The present invention relates to the formation and processing of semiconductor wafers. More particularly, the present invention relates to an elevated containment structure in the shape of a ring located around the peripheral edge of a wafer and methods of forming and using such a structure.
2. State of the Art
Solid state electronic devices are manufactured on a mass scale from wafers of semiconductor material that are singulated to provide multiple individual semiconductor dice. Integrated circuitry is formed on a wafer by depositing successive layers of conductive material separated from each other by layers of dielectric insulating material. After deposition, each layer of material is formed into a specific pattern comprising a level of the integrated circuitry, and another layer of material is added. Patterning of each layer of material is typically accomplished with a mask and etch process, wherein a photoresist is applied over the layer of material to be patterned. Portions of the photoresist are exposed by using an optical system to project light or other forms of radiant energy onto the photoresist in a pattern corresponding to the circuitry, and either the exposed or the unexposed portions of the photoresist (depending on the photoresist type) are removed to uncover the underlying layer of material. An etchant is then applied to form the layer of material into the desired circuit pattern. The remaining photoresist is removed, and the next layer of material is deposited. The process is repeated until the levels of circuitry are complete. In this manner, a large number of electronic devices may be simultaneously, formed at the wafer level, thereby increasing manufacturing output.
Another benefit in terms of manufacturing output that is provided by forming multiple electronic devices from wafers is that device packaging may be carried out at the wafer level to form what are commonly referred to as “chip scale packages” (CSPs). CSP structures typically comprise protective layers of a polymer or other material films adhered directly to at least the active surface of a semiconductor die to seal it from the environment. When multiple electronic devices are contained in a wafer, the active surface of the wafer may be coated to provide multiple electronic devices with the aforementioned sealing layer in a single operation, with subsequent singulation of the wafer into individual CSPs. One process for forming CSP sealing layers on a wafer is stereolithography (STL). STL, as conventionally practiced, involves the formation of solid structures by selectively curing volumes of a liquid polymer or other curable liquid material. Depending on the liquid material composition, curing may be accomplished by exposure to irradiation of selected wavelengths of light or other forms of radiant energy, for instance, when curing a material susceptible to initiation of cross-linking by exposure to ultraviolet (UV) radiation. In this manner, CSP sealing layers may be simultaneously formed on multiple electronic devices by depositing and selectively curing one or more layers of a liquid polymer or other liquid sealing material over at least the active surface of a wafer.
While manufacturing electronic devices in wafer form improves efficiency, it raises other processing issues. Projecting a large circuit pattern for multiple electronic devices on a wafer using the above described mask and etch process, for instance, increases the difficulty in maintaining focus of the radiant energy used to expose the photoresist. This problem is exacerbated by the fact that as circuit densities increase, more precise resolution is required for the circuit pattern being projected onto the photoresist. The resolution of an optical system is determined by the equation R=k1 (λ/NA), where k1 is a constant related to process parameters and λ is the wavelength of the projected radiant energy. NA is the numerical aperture of the optical system projection lens, which is dependent in part on the refractive index of the medium surrounding the lens through which the radiant energy is projected. Accordingly, the minimum resolvable feature of a circuit pattern projected by an optical system is limited by these resolution factors.
One approach to improve focusing has been to alter the refractive index of the medium surrounding the optical system lens by using immersion lithography. In immersion lithography, the space between the optical system lens and the photoresist on a wafer is filled with a liquid such as water, with the radiant energy for exposing the photoresist being projected therethrough. Because the liquid has a higher refractive index than air, the effective numerical aperture value of the optical system lens is increased and improves resolution. Exemplary immersion lithography optical systems for patterning photoresists on semiconductor wafers are described in U.S. Pat. No. 5,610,683 to Takahashi and European Patent EP 0 023 231 A1 to Tabarelli et al., the disclosures of each of which are incorporated herein by reference. Although these optical systems provide improved resolution for forming circuit patterns on wafers, they involve the use of special tanks or cassettes that surround a wafer in order to contain the liquid for immersion lithography. Major modifications must be made to optical systems in order to accommodate such containment structures, and positioning the additional tanks or cassettes within the optical system may reduce throughput and create a process bottleneck.
Other processing issues related to manufacturing electronic devices in wafer form may also be encountered when forming the above-described CSP sealing layers. In order to coat a wafer with a sealing layer, for example, a liquid polymer or other liquid sealing material must be deposited onto the active surface of the wafer and subsequently cured to form the sealing layer. One known coating method is to submerge a wafer to consecutive depths below the surface of a liquid sealing material contained within a tank, and selectively cure layers of the liquid sealing material overlying the wafer active surface at each depth using the above-described STL process. Examples of such an STL coating method are described in U.S. Pat. No. 6,432,752 to Farnworth and U.S. Pat. No. 6,326,698 to Akram, the disclosures of each of which are incorporated herein by reference. Positioning of the wafer at consecutive depths below the surface of the liquid sealing material may be time consuming, however, and it is often difficult to control the thickness of the liquid sealing material overlying the wafer active surface.
An alternative coating method is to deposit the liquid sealing material onto the wafer active surface using spin coating. In spin coating, a liquid sealing material is deposited on a wafer and spread across the wafer active surface by spinning the wafer on a rotating chuck. While spin coating allows for efficient deposition of the liquid sealing material, it may be difficult to achieve uniform application across the wafer active surface, especially when forming thicker CSP sealing layers. Furthermore, since a wafer must typically be moved to another location to cure the liquid sealing material applied by spin coating, there is the possibility that the uncured liquid sealing material will roll off the wafer active surface during handling.
In view of the foregoing discussion of the prior art, a simple and efficient way is needed to contain liquid over the active surface of a wafer during processing operations such as immersion lithography and forming CSP sealing layers.